A pre-amplifier is used for a light receiver in an optical communication system. The optical communication system is, for example, asynchronous transfer mode-passive optical network (hereinafter, “ATM-PON”), which is an international standard communication system according to the ITU-T recommendation G.983. According to this system, one station can realize a point-to-multi-point transmission with a plurality of subscriber apparatuses with the time division multiplexing, so that transmission can be realized at low cost.
A pre-amplifier is disclosed, for example, in Japanese Patent Application Laid-open Publication No. 2000-315923 (i.e., burst light receiving circuit). FIG. 4 is a circuit diagram of the conventional gain switching circuit for a pre-amplifier. FIG. 5 is a time chart of operation of the conventional gain switching circuit. FIG. 6 is a flowchart of operation of the conventional gain switching circuit.
A photodetector 1 converts a light signal into an electric signal. A pre-amplifier 2 receives the electric signal (i.e., current signal) A. This pre-amplifier 2 includes an operation amplifier 2a and a feedback resistor 2b. The pre-amplifier 2 is a transimpedance amplifier (hereinafter, “TIA”) that amplifies an input current signal and outputs a voltage signal.
The feedback resistor 2b of the TIA 2A is connected in parallel with a serial circuit of a resistor 5 and a diode 8, a serial circuit of a resistor 6 and a switching MOS transistor 9, and a serial circuit of a resistor 7 and a switching MOS transistor 10 respectively.
A gain switching circuit 31 has identification circuits 11 and 12 and flip-flop circuits 13 and 14, thereby to receive an output (i.e., voltage signal) b from the TIA 2, and control ON and OFF of the MOS transistors 9 and 10 according to the output level. The gain switching circuit 31 switches over a feedback resistance of the TIA 2.
In other words, the output (i.e. voltage signal) b from the TIA 2 is input to positive phase input terminals (+) of the identification circuits 11 and 12. A reference voltage V1 is input to a negative phase input terminal (−) of the identification circuit 11, and a reference voltage V2 (V1<V2) is input to a negative phase input terminal (−) of the identification circuit 12.
An output terminal of the identification circuit 11 is connected to a clock input terminal C of the flip-flop circuit 13, and a data input terminal D of the flip-flop circuit 13 is connected to a power source VH. A signal d output from a data output terminal Q of the flip-flop circuit 13 is applied to a gate electrode of the MOS transistor 9, thereby to turn ON the MOS transistor 9. As a result, the resistor 6 is connected in parallel to the feedback resistor 2b. 
An output terminal of the identification circuit 12 is connected to a clock input terminal C of the flip-flop circuit 14, and a data input terminal D of the flip-flop circuit 14 is connected to the power source VH. A signal e output from a data output terminal Q of the flip-flop circuit 14 is applied to a gate electrode of the MOS transistor 10, thereby to turn ON the MOS transistor 10. As a result, the resistor 7 is connected in parallel to the feedback resistor 2b. 
An external reset signal (RESET) c is input to a reset terminal R of the flip-flop circuits 13 and 14 respectively. The reset signal (RESET) c is input prior to the input of a light burst signal. Therefore, the flip-flop circuits 13 and 14 are initialized at the head of each burst signal. Accordingly, the MOS transistors 9 and 10 are in the OFF (open) operation state at the head of each burst signal.
The operation of the conventional gain switching circuit will be explained next with reference to FIG. 5. For the sake of convenience of explanation, it is assumed that the diode 8 does not operate.
In FIG. 5, (a) is a waveform diagram of current output from the photodetector 1, that is, a waveform of current input to the TIA 2. Light burst signals are input to the photodetector 1 in the order of bursts #1, #2, and #3. The bursts #1, #2, and #3 are data signals having a bit pattern of “1010” respectively. The amplitude increases in this order.
(b) is a waveform diagram of a relationship between a waveform of an output voltage (Vout) b from the TIA 2 and the reference voltages V1 and V2. The output voltage (Vout) b from the TIA 2 to the burst #1 is at the reference voltage V1 or below. The output voltage (Vout) b from the TIA 2 to the burst #2 exceeds the reference voltage V1, but does not exceed the reference voltage V2. The output voltage (Vout) b from the TIA 2 to the burst #3 exceeds the reference voltage V2.
(c) is a waveform diagram of the reset signal (RESET) c. The reset signal (RESET) c is input at the head of the bursts #1, #2, and #3 respectively. Accordingly, the flip-flop circuits 13 and 14 are at the initialized state at the head of each burst signal. The MOS transistors 9 and 10 are in the OFF (open) operation state at the head of each burst signal. In other words, the TIA 2 is in the conversion gain determined by the feedback resistor 2b at the head of each burst signal.
(d) and (e) are waveform diagrams of the operation of the identification circuits 11 and 12 and the flip-flop circuits 13 and 14. In (d), as the amplitude of the burst #1 output from the TIA 2 is at the reference voltage V1 or below, the identification circuit 11 does not operate, but the TIA 2 amplifies the burst #1 in the original conversion gain.
As the amplitude of the first bit of the burst #2 exceeds the reference voltage V1, the identification circuit 11 sets the output level from the level “0” to the level “1”, and holds this level until when the reset signal (RESET) c is input. A signal d of the level “1” is output from the data output terminal Q of the flip-flop circuit 13, and the MOS transistor 9 is turned ON, thereby to connect the resistor 6 in parallel with the feedback resistor 2b. As a result, in the burst #2, the conversion gain of the TIA 2 is switched over from the original conversion gain into a small conversion gain that is determined according to a feedback resistance due to the parallel connection between the feedback resistor 2b and the resistor 6.
As the amplitude of the first bit of the burst #3 exceeds the reference voltage V1, the identification circuit 11 sets the output level from the level “0” to the level “1”. A signal d of the level “1” is output from the data output terminal Q of the flip-flop circuit 13, and the MOS transistor 9 is turned ON, thereby to connect the resistor 7 in parallel with the feedback resistor 2b. 
In (e), as the amplitude of the first bit of the burst #3 exceeds the reference voltage V2, the identification circuit 12 sets the output level from the level “0” to the level “1”. A signal e of the level “1” is output from the data output terminal Q of the flip-flop circuit 14, and the MOS transistor 10 is turned ON, thereby to connect the resistor 7 in parallel with the feedback resistor 2b. As a result, in the burst #3, the conversion gain of the TIA 2 is switched over from the original conversion gain into a smaller conversion gain that is determined according to a feedback resistance due to the parallel connection between the feedback resistor 2b and the resistors 6 and 7.
The flowchart shown in FIG. 6 summarizes the above operation. Referring to FIG. 6, at step S81, the gain switching circuit 31 receives the reset signal (RESET) at the head of the burst signal. In other words, when the reset signal (RESET) is input, the flip-flop circuits 13 and 14 are reset, and the MOS transistors 9 and 10 are in the OFF state, thereby to return the gain of the TIA 2 to the original conversion gain.
When the light burst signal is input to the photodetector 1 in this state, the output level identification circuits 11 and 12 of the TIA 2 detect whether these signals exceed the respective threshold values V1 and V2 (step S82).
When the output from the TIA 2 is at or below the reference voltage V1 (No at step S83), the gain switching circuit 31 does not turn ON the MOS transistor 9. When the output from the TIA 2 exceeds the reference voltage V1 (Yes at step S83), the gain switching circuit 31 does not turn ON the MOS transistor 9, and maintains the ON state of this transistor (step S84).
When the output from the TIA 2 is lower than the reference voltage V2 (No at step S85), the gain switching circuit 31 does not turn ON the MOS transistor 10. When the output from the TIA 2 is at or above the reference voltage V2 (Yes at step S85), the gain switching circuit 31 does not turn ON the MOS transistor 10, and maintains the ON state of this transistor (step S86).
As explained above, when the output level of the TIA 2 is at or below the reference voltage V1, the conventional gain switching circuit for a pre-amplifier sets the conversion gain of the TIA 2 to the original gain. When the output level of the TIA 2 exceeds the reference voltage V1 and is at or below the reference voltage V2, the conventional gain switching circuit turns ON only the MOS transistor 9, and connects the resistor 6 in parallel with the feedback resistor 2b. When the output level of the TIA 2 exceeds the reference voltage V2, the conventional gain switching circuit turns ON both the MOS transistors 9 and 10, and connects the resistors 6 and 7 in parallel with the feedback resistor 2b. The conventional gain switching circuit switches over the conversion gain of the TIA 2 in this way.
However, as can be understood from the control flow shown in FIG. 6, when the amplitude of the output voltage from the TIA exceeds the reference voltage, the conventional gain switching circuit turns ON the MOS transistor without exception. Therefore, when various kinds of waveform distortions such as ringing, amplitude fluctuation, and signal sag occur, the conventional gain switching circuit does not always switch the gain at the head of the burst signal. There is a possibility that the conventional gain switching circuit switches over the gain at an optional bit position within the burst signal, which makes it difficult to follow the threshold value. Further, depending on the waveform distortion or the like, the conventional gain switching circuit may set the conversion gain to a level different from a target gain.
These problems will be explained in detail below with reference to FIG. 4 and FIG. 6 to FIG. 8. FIG. 7 is a time chart illustrating an example of a malfunctioning of the conventional gain switching circuit shown in FIG. 4. FIG. 8 is a graph of input-output characteristic of the TIA 2 as the pre-amplifier shown in FIG. 4.
In FIG. 7, (a′) is a waveform of a current output from the photo detector 1, that is, a waveform of a current input to the TIA 2. This waveform is of a state that light burst signals of a first burst and a second burst are input in this order to the photo detector 1. The first burst and the second burst are data signals having a bit pattern of “1010” respectively. The amplitude increases in this order. A waveform distortion such as a large ringing is observed at a rising portion of each bit “1”.
(b′) is an illustration of a relationship between a waveform of the output voltage (Vout) from the TIA 2 and the reference voltages V1 and V2. In a waveform of the output from the TIA 2 to the first burst, a waveform indicated by a dotted line 61 is a target signal waveform, which is substantially at the same level as the reference voltage V1. On the other hand, a waveform indicated by a solid line 62 becomes a cause of generating a malfunctioning. This waveform may or may not exceed the reference voltage V1 at random due to the ringing or the amplitude fluctuation.
In a waveform of the output from the TIA 2 to the second burst, a waveform indicated by a dotted line 63 is a target signal waveform, which exceeds the reference voltage V1 and does not exceed the reference voltage V2. On the other hand, a waveform indicated by a solid line 64 becomes a cause of generating a malfunctioning. The first bit has a large signal sag Td that exceeds the reference voltage V2. Each bit thereafter has a portion large dropped to below the reference voltage V1.
(c′) is an illustration of a waveform of a reset signal (RESET). The reset signal (RESET) is input at the head of the first burst and the second burst respectively. Based on this, the flip-flop circuits 13 and 14 are initialized at the head of each burst signal. The MOS transistors 9 and 10 are in the OFF (closed) operating state at the head of each burst signal. In other words, at the head of each burst signal, the TIA 2 is in the original conversion gain of the TIA 2 that is determined by the feedback resistor 2b. 
(d′) and (e′) are waveform diagrams for explaining the operations of the identification circuits 11 and 12, and the flip-flop circuits 13 and 14. Referring to (d′), when the waveform of a signal output from the TIA 2 to the first burst is the target signal waveform indicated by the dotted line 61 of (b′), the amplitude of the first bit exceeds the reference voltage V1. Therefore, the identification circuit 11 can correctly recognize this signal waveform at the first bit position. Accordingly, the MOS transistor 9 can be turned ON at the timing of the first bit.
However, when the waveform of a signal output from the TIA 2 to the first burst is that indicated by the solid line 62 of (b′), the amplitude exceeds the reference voltage V1 at not only the first bit position but also at an optional bit position thereafter. Accordingly, the MOS transistor 9 can be turned ON at an optional bit position within the burst signal. For example, as indicated by a solid line 66, the MOS transistor 9 is turned ON at a fifth bit position, which causes the conversion gain to be switched over in the middle of the burst signal.
Referring to (e′), when the waveform of a signal output from the TIA 2 to the second burst is the target signal waveform indicated by the dotted line 63 of (b′), the amplitude of the first bit exceeds only the reference voltage V1 and does not exceed the reference voltage V2. Therefore, only the identification circuit 11 operates, and the identification circuit 12 does not operate. In this case, as indicated by a dotted line 67, the MOS transistor maintains the OFF state from the first bit timing, and only the MOS transistor 9 are ON as in (d′).
However, when the waveform of a signal output from the TIA 2 to the first burst is the signal waveform having the large sag as indicated by the solid line 64 in (b′), the amplitude of the first bit exceeds the reference voltage V2. Therefore, the identification circuit 12 can correctly recognize this signal waveform at the first bit position as indicated by a solid line 68. Accordingly, the MOS transistor 10 can be turned ON at the timing of the first bit. In this case, the conversion gain obtained by connecting only the resistor 6 to the feedback resistor 2b in parallel is the target gain. However, the resistor 7 is further set to the conversion gain different from the target gain when the resistor 7 is connected in parallel, which makes the output amplitude smaller than the target amplitude.
FIG. 8 is an explanatory diagram of the above operation using input-output characteristic of the TIA 2. The characteristics 71, 72, and 73 correspond to the operation shown in FIG. 5. In other words, the characteristic 71 is input-output characteristic when the TIA 2 operates in the original conversion gain as shown by the burst #1. Next, in the burst #2, the MOS transistor 9 is ON at the gain switching point A as the timing when the amplitude exceeds the reference voltage V1. Therefore, the gain is switched over to change the characteristic to the input-output characteristic 72. Next, in the burst #3, the MOS transistors 9 and 10 are ON at the gain switching point B as the timing when the amplitude exceeds the reference voltage V2. Therefore, the gain is switched over to change the characteristic to the input-output characteristic 73.
On the other hand, in the operation shown in FIG. 7, the first burst is at a level equivalent to the reference voltage V1, that is, a level near the gain switching point A. Therefore, the amplitude exceeds the reference voltage V1 at an optional bit position not only at the first bit position due to the ringing and the amplitude fluctuation of the waveform. Consequently, t he MOS transistor 9 is turned ON at an optional bit position within the burst signal.
In the second burst, when the first bit exceeds the reference voltage V2 by error due to the ringing of the waveform or the like, the MOS transistors 9 and 10 are turned ON at the first bit position. Therefore, the gain switching point B shifts to a gain switching point B′ at the small amplitude side, and the characteristic 73 changes to a characteristic 74 that starts at the gain switching point B′ at the small amplitude side. Consequently, the output amplitude becomes much smaller than the target amplitude.